(a) Field of the Invention
The present invention relates to a semiconductor charge transfer device, and more particularly it pertains to a charge transfer device utilizing the principles of static induction transistor.
(b) Background of the Invention
Charge transfer devices may be divided into the following two types: minority carrier transfer type and majority carrier transfer type.
Known minority carrier transfer type charge transfer devices have the drawback that they tend to ignore transfer of stored charge (transfer loss) as viewed from the principles of such devices.
Also, in known carrier transfer, there is introduced in some part of the transfer process a movement of minority carriers due to diffusion. Such introduction determines the upper limit of the speed of transfer. Moreover, minority carriers usually move in the vicinity of the interface between the semiconductor body and the insulating film. Therefore, these minority carriers are susceptible to the influence of the surface such as surface mobility and trap. In order to overcome these drawback and inconveniences, there has been proposed majority carrier transfer type charge coupled devices. In majority carrier transfer type charge coupled devices, there is produced a depletion layer around the charge-storing region, and the transfer of those majority carriers is performed by wrapping the charge carriers with this depletion layer. Since this transfer is of the type to expel charge carriers by the repulsive field, there exists a problem in the efficiency of transfer.
The static induction transistor (SIT) proposed by the present inventor is a transistor designed to be operative so that the travel of the charge carriers which flow from the source region to the drain region is controlled by a potential barrier which, in turn, is controlled by both the gate potential and the drain potential. This potential barrier is formed by a saddle portion of the potential distribution, and the charge carriers flow in the transverse direction along the lowest portion of the saddle portion (low potential region) after passing the extremal point located intermediary in the saddle portion. By selecting the impurity concentration of the channel region at a low value so as to enable the channel region to become easily depleted and to produce a saddle-shaped potential distribution without leaving an elongated neutral region, and by reducing the distance from the source region to the saddle portion (intrinsic gate), a non-saturating type current-voltage characteristic is materialized. The gate structure of SIT has, as its main object, to transmit a potential to the channel region, and may be of the junction type, Schottky type or insulated-electrode type. The conductivity type of the channel region may be the same with that of the source region, or it may have a conductivity type opposite to that of the source region. In either case, a voltage applied between the source region and the drain region has a tendency to produce a monotonically decreasing potential gradient between the source region and the drain region and to allow a flow of current. Such current flow is controlled by modulating the intermediately-located potential distribution by a source-to-gate voltage. In case the channel region has a conductivity type same as that of the source region, a high potential portion (potential barrier) is produced within the channel region by a total gate potential including the build-in potential. Namely, the total gate potential pulls up the potential of the channel region. This potential barrier is controlled by a gate voltage and a drain voltage. The length of this potential barrier in the source-to-drain direction is arranged to be sufficiently small so as to let those carriers which have passed over this potential barrier flow quickly toward the drain region.
In case the channel region has a conductivity type opposite to the source region, the length of the channel region is arranged to be small (short-channel) and the impurity concentration of the channel region is arranged to be low to ensure that the channel region located between the source region and the drain region is rendered to the punching-through stage, i.e. depleted, by the application of a drain voltage so that the potential barrier located in the foreground of the source due to the pn junction can be controlled by the application of a drain voltage, and concurrently therewith the width of this channel region is selected so that the influence of the gate voltage applied will extend throughout the overall width of the channel region and will control the height of the potential barrier.
Because of the fact that, in the main operative state, the major portion of the channel region is depleted, the operation principles of the device wherein the channel region has a conductivity type opposite to that of the source region is substantially the same as that of the device wherein the channel region has a conductivity type same as that of the source region, except that the space charge has a polarity identical with or different from that of the charge carriers which constitute a current.